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| ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet Features * * * * * * * * * * * * Digital compensation of sensor offset, sensitivity, temperature drift and non-linearity Accommodates nearly all bridge sensors types (signal spans from 1 up to 275mV/V processable) Digital one-shot calibration: quick and precise Selectable temperature compensation reference: bridge, thermistor, internal diode or external diode Output options: voltage (0...5V), current (4...20mA), PWM, I2C, SPI, ZACwireTM (onewire-interface), alarm Adjustable output resolution (up to 15 bits) versus sampling rate (up to 3.9kHz) Selectable bridge excitation: ratiometric voltage, constant voltage or constant current Input channel for separate temperature sensor Sensor connection and common mode check (Sensor aging detection) operation temperature, depending on product version, up to -40...+125C (-55...+150C derated) Supply voltage +2.7V...+5.5V Available in SSOP16 or as die PRELIMINARY Brief Description ZMD31050 is a CMOS integrated circuit for highlyaccurate amplification and sensor-specific correction of bridge sensor signals. The device provides digital compensation of sensor offset, sensitivity, temperature drift and non-linearity by a 16-bit RISC micro controller running a correction algorithm with correction coefficients stored in non-volatile EEPROM. The ZMD31050 accommodates virtually any bridge sensor (e.g. piezo-resistive, ceramic-thickfilm or steel membrane based). In addition, the IC can interface a separate temperature sensor. The bi-directional digital interfaces (I2C, SPI, ZACwireTM) can be used for a simple PC-controlled one-shot calibration procedure, in order to program a set of calibration coefficients into an on-chip EEPROM. Thus a specific sensor and a ZMD31050 are mated digitally: fast, precise and without the cost overhead associated with laser trimming, or mechanical potentiometer methods. Application kit available (SSOP16 samples, calibration PCB, calibration software, technical documentation) Support for industrial mass calibration available Quick circuit customization possible for large production volumes Benefits * * * No external trimming components required PC-controlled configuration and calibration via digital bus interface - simple, low cost High accuracy (0.1% FSO @ -25...85C; 0.25% FSO @ -40...125C) Application Circuit (Examples) Fig.1: Ratiometric measurement with voltage output, temperature compensation via external diode Fig.2: Two wire 4...20mA (5...40V) configuration, temperature compensation via internal diode Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 1/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY Contents 1. CIRCUIT DESCRIPTION ............................................................................................................3 1.1 SIGNAL FLOW ...........................................................................................................................3 1.2 APPLICATION MODES.................................................................................................................4 1.3 ANALOG FRONT END (AFE) .......................................................................................................5 1.3.1. Programmable Gain Amplifier ........................................................................................5 1.3.2. Analogue Sensor Offset Compensation - Extended Zero Shift (XZC)............................5 1.3.3. Measurement Cycle Realized by Multiplexer .................................................................6 1.3.4. Analog-to-Digital Converter............................................................................................7 1.4 SYSTEM CONTROL ....................................................................................................................8 1.5 OUTPUT STAGE.........................................................................................................................9 1.5.1. Analog Output..............................................................................................................10 1.5.2. Comparator Module (ALARM Output)..........................................................................10 1.5.3. Serial Digital Interface..................................................................................................10 1.6 VOLTAGE REGULATOR.............................................................................................................11 1.7 ERROR DETECTION .................................................................................................................11 2. 3. 4. 5. APPLICATION CIRCUIT EXAMPLES ......................................................................................13 ESD/LATCH-UP-PROTECTION ...............................................................................................13 PIN CONFIGURATION AND PACKAGE...................................................................................14 IC CHARACTERISTICS............................................................................................................15 5.1 ABSOLUTE MAXIMUM RATINGS.................................................................................................15 5.2 OPERATING CONDITIONS (VOLTAGES RELATED TO VSS) ......................................................15 5.3 BUILD IN CHARACTERISTICS.....................................................................................................16 5.3.8 Cycle Rate versus A/D-Resolution ......................................................................................17 5.3.9 PWM Frequency .................................................................................................................17 5.4 ELECTRICAL PARAMETERS (VOLTAGES RELATED TO VSS) ....................................................18 5.5 INTERFACE CHARACTERISTICS .................................................................................................19 6. 7. 8. 9. TEST ........................................................................................................................................20 RELIABILITY ............................................................................................................................20 CUSTOMIZATION ....................................................................................................................20 RELATED DOCUMENTS .........................................................................................................20 Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 2/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 1. 1.1 Circuit Description Signal Flow Fig.3: Block diagram of ZMD31050 PGA MUX ADC CMC DAC FIO1 FIO2 SIF PCOMP EEPROM TS ROM PWM programmable gain amplifier multiplexer analog-to-digital converter calibration microcontroller digital-to-analog converter flexible I/O 1: analog out (voltage/current), PWM2, TM ZACwire (one-wire-interface) flexible I/O 2: PWM1, SPI data out, SPI slave select, Alarm1, Alarm2 serial interface: I2C data I/O, SPI data in, clock programmable comparator for calibration parameters and configuration on-chip temperature sensor (pn-junction) for correction formula and -algorithm PWM module The ZMD31050's signal path is partly analog (blue) and partly digital (red). The differential signal from the bridge sensor is pre-amplified by the programmable gain amplifier (PGA). The Multiplexer (MUX) transmits the signals from bridge sensor, external diode or separate temperature sensor to the ADC in a certain sequence (instead of the temp. diode the internal pnjunction (TS) can be used optionally). Afterwards the ADC converts these signals into digital values. The digital signal correction takes place in the calibration micro-controller (CMC). It is based on a special correction formula located in the ROM and on sensor-specific coefficients (stored into the EEPROM during calibration). Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 3/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY Dependent on the programmed output configuration the corrected sensor signal is output as analog value, as PWM signal or in digital format (SPI, I2C, ZACwireTM ). The output signal is provided at 2 flexible I/O modules (FIO) and at the serial interface (SIF). The configuration data and the correction parameters can be programmed into the EEPROM via the digital interfaces. The modular circuit concept enables fast custom designs varying these blocks and, as a result, functionality and die size. 1.2 Application Modes For each application a configuration set has to be established (generally prior to calibration) by programming the on-chip EEPROM regarding to the following modes: - - - - - - - - - - Sensor channel Sensor mode: ratiometric voltage or current supply mode. Input range: The gain of the analog front end has to be chosen with respect to the maximum sensor signal span and the zero point of the ADC has to be set with respect to the possible input voltage range Additional offset compensation: The extended analog offset compensation has to be enabled if required, e.g. if the sensor offset voltage is near to or larger than the sensor span. Resolution/response time: The A/D converter has to be configured for resolution and converting scheme (first or second order). These settings influence the sampling rate, signal integration time and this way the noise immunity Sample order: The order and interval of multiplexed measurements (pressure, temperature, auto zero) has to be set Ability to invert the sensor bridge inputs Analog output Choice of output method (voltage value, current loop, PWM) for output register 1. Optional choice of output register 2: PWM module via IO1 or alarm out module via IO1/2. Digital communication: The preferred protocol and its parameter have to be set. Temperature The temperature measure channel for the temperature correction has to be chosen. Optional: the temperature measure channel as the second output has to be chosen. Supply voltage : For non-ratiometric output the voltage regulation has to be configured. Note: Not all possible combinations of settings are allowed (see section 1.5). The calibration procedure must include - the set of coefficients of calibration calculation and depending on configuration, - the adjustment of the extended offset compensation, - the zero compensation of temperature measurement, - the adjustment of the bridge current and if necessary - the set of thresholds and delays for the alarms, - the reference voltage. Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 4/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 1.3 Analog Front End (AFE) PRELIMINARY The analog front end consists of the programmable gain amplifier (PGA), the multiplexer (MUX) and the analog-to-digital converter (ADC). 1.3.1. Programmable Gain Amplifier The following tables show the adjustable gains, the processable sensor signal spans and the allowed common mode range. Max. span Input range in mV/V in % VDDA 1 420 2 43 - 57 2 280 3 38 - 62 3 210 4 43 - 57 4 140 6 40 - 59 5 105 8 38 - 62 6 70 12 40 - 59 7 52,5 16 38 - 62 8 35 24 40 - 59 9 26,3 32 38 - 62 10 14 50 43 - 57 11 9,3 80 40 - 59 12 7 100 38 - 62 13 2,8 280 21 - 76 Table 1: Adjustable gains, resulting sensor signal spans and common mode ranges 1.3.2. Analogue Sensor Offset Compensation - Extended Zero Shift (XZC) No. PGA Gain The ZMD31050 supports two methods of sensor offset cancellation (zero shift): * * digital offset correction analogue cancellation for large offset values (up to 300% of span) Digital sensor offset correction will be processed at the digital signal correction/conditioning by the CMC. Analogue sensor offset precompensation will be needed for compensating of large offset values, which would be overdrive the analogue signal path by uncompensated gaining. For analogue sensor offset precompensation an compensation voltage will be added in the analogue pregaining signal path (coarse offset removal). The analog offset compensation in the AFE can be adjusted by 6 EEPROM bits. It allows a zero point shift up to 300% of the processable signal span. The zero point shift of the temperature measurements can also be adjusted by 6 EEPROM bits. Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 5/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PGA gain Max. span in mV/V Offset shift per step in % full span 15% 9% 15% 9% 6% 9% 6% 9% 6% 15% 9% 6% 1% PRELIMINARY Approx. maximum offset shift in mV/V +/- 9 +/- 8 +/- 18 +/- 16 +/- 14 +/- 33 +/- 29 +/-66 +/- 59 +/- 230 +/-220 +/- 180 +/- 87 420 280 210 140 105 70 52,5 35 26,3 14 9,3 7 2,8 2 3 4 6 8 12 16 24 32 50 80 100 280 Table 2 : Extended zero shift ranges 1.3.3. Measurement Cycle Realized by Multiplexer The Multiplexer selects, depending on EEPROM settings, the following inputs in a certain sequence. Bridge temperature signal measured by external diode Bridge temperature signal measured by internal pn-junction Bridge temperature signal measured by bridge resistors Separate temperature signal measured by external thermistor Internal offset of the input channel measured by input short circuiting Pre-amplified bridge sensor signal Start routine The complete measurement cycle is controlled by the CMC. The cycle diagram at the right shows its principle structure. The EEPROM adjustable parameters are: Pressure measurement count, n=<1,2,4,8,16,32,64,128> Enable temperature measurement 2, e2=<0,1> n 1 n 1 n 1 n * e2 e2 e2 * Pressure measurement Temp 1 auto zero Pressure measurement Temp 1 measurement Pressure measurement Pressure auto zero Pressure measurement Temp 2 auto zero Temp 2 measurement After Power ON the start routine is called. It contains the pressure and auto zero measurement. When enabled it measures the temperature and its auto zeros. n * e2 * Pressure measurement Fig. 4: Measurement cycle ZMD31050 Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 6/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 1.3.4. Analog-to-Digital Converter PRELIMINARY The ADC is a charge balancing converter in full differential switched capacitor technique. It can be used as first or second order converter: In the first order mode it is inherently monotone and insensitive against short and long term instability of the clock frequency. The conversion time depends on the desired resolution and can be roughly calculated by: tc= 2R s The available resolutions are R=<9,10,11,12,13,14,15>. The result of the AD conversion is a relative counter result corresponding to the following equation: VIN /VREF = ZOUT/N - ZS ZOUT: N: VIN: VREF: ZS: number of counts (result of the conversion) total number of counts (=2R) differential input voltage of ADC differential reference voltage zero point shift (ZS=1/16, 1/8, 1/4, 1/2, controlled by the EEPROM content) With the ZS value a sensor input signal can be shifted in the optimal input range of the ADC. In the second order mode two conversions are stacked with the advantage of much shorter conversion time and the drawback of a lower noise immunity caused by the shorter signal integration period. The conversion time at this mode is roughly calculated by: tc= 2(R+3)/2 s The available resolutions are R=<10,11,12,13,14,15>. The result of the AD conversion is a relative counter result corresponding to the following equations: VIN /VREF = ZOUT/N - ZS ZOUT = Z1 * (N2/2) + Z2 N = N1 * N2 Z1: Z2: N1: N2 VIN: VREF: ZS: number of counts (result of the 1 conversion) number of counts (result of the 2nd conversion) total number of counts 1st conversion (=2(R+1)/2) nd (R+1)/2 total number of counts 2 conversion (=2 ) differential input voltage of ADC differential reference voltage zero point shift (RS=1/16, 1/8, 1/4, 1/2, controlled by CMC) st Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 7/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY Note: The AD conversion time is only a part of a whole sample cycle. Thus the sample rate is lower then the AD conversion rate. ADC Max. Output Resolution Sample Rate Order Resolution* Digital Analog PWM Bit Bit Bit Bit Hz 1 9 9 9 9 1302 10 10 10 10 781 11 11 11 11 434 12 12 11 12 230 13 13 11 12 115 14 14 11 12 59 15 15 11 12 30 2 10 10 10 10 3906 11 11 11 11 3906 12 12 11 12 3906 13 13 11 12 1953 14 14 11 12 1953 15 15 11 12 977 Table 2: Output resolution versus sample rate *ADC Resolution should be 1 or 2 Bits higher then applied Output Resolution 1.4 System Control The system control has the following features: Control of the I/O relations and of the measurement cycle regarding to the EEPROM-stored configuration data 16 bit correction calculation for each measurement signal using the EEPROM stored calibration coefficients and ROM-based algorithms Started by internal POC, internal clock - generator or external clock For safety improvement the EEPROM data are proved with a signature within initialization procedure, the registers of the CMC are steadily observed with a parity check. Once an error is detected, the error flag of the CMC is set and the outputs are driven to a diagnostic value Note: The conditioning includes up to third order sensor input correction. The available adjustment ranges depend on the specific calibration parameters, a detailed description will be issued later. To give a rough idea: Offset compensation and linear correction are only limited by the loose of resolution it will cause, the second order correction is possible up to about 30% full scale difference to straight line, third order up to about 20%. The temperature calibration includes first and second order correction and should be fairly sufficient in all relevant cases. Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 8/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 1.5 Output Stage Used serial IF No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 IC X X X X X X X X X X X X X X X X X X X X X X X X X X X Analog Analog Analog PWM2 PWM2 PWM2 Analog Analog Analog Analog Analog Analog PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 ALARM1 PWM1 PWM1 Data out Data out ALARM1 Data out PWM1 Data out Data out ALARM1 Data out PWM1 Data out Data out ALARM1 Data out PWM1 ALARM2 Slave select Slave select Slave select Slave select Slave select Slave select Slave select Slave select Slave select ALARM1 ALARM2 ALARM2 ALARM1 PWM1 PWM1 ALARM2 ALARM1 ALARM2 ALARM2 ALARM1 PWM1 PWM1 ALARM2 ALARM1 ALARM2 ALARM2 2 PRELIMINARY Used I/O pins OUT IO1 IO2 SDA Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data in Data in Data in Data in Data in Data in Data in Data in Data in - SPI The ZMD31050 provides the following I/O pins: OUT, IO1, IO2 and SDA. Via these pins the following signal formats can be output: Analog (voltage/current), PWM, Data (SPI/I2C), Alarm. The following values can be provided at the O/I pins: bridge sensor signal, temperature signal 1, temperature signal 2, alarm. Note: The Alarm signal only refers to the bridge sensor signal, but never to a temperature signal. Due to the necessary pin sharing there are restrictions to the possible combinations of outputs and interface connections. The table beside gives an overview about possible combinations. Note: In the SPI mode the pin IO2 is used as Slave select. Thus no Alarm 2 can be output in this mode. Table 3: Output configurations overview Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 9/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 1.5.1. Analog Output For the analog output 3 registers of 12 bit depth are available, which can store the actual pressure and the results of temperature measurement 1 and 2. Each register can be independently switched to one of two output slots connected to the Pin OUT and IO1 respectively. In these output slots different output modules are available according to the following table: Output slot: OUT Voltage x PWM x Table 5:Analog output configuration IO1 x The Voltage module consists of an 11bit resistor string - DAC with buffered output and a subsequent inverting amplifier with class AB rail-to-rail OPAMP. The two feedback nets are connected to the Pins FBN and FBP. This structure offers wide flexibility for the output configuration, for example voltage output and 4 to 20 mA current loop output. To short circuit the analog output against VSS or VDDA does not damage the ZMD31050. The PWM module provides pulse streams with signal dependent duty cycle. The PWM - frequency depends on resolution and clock divider. The maximum resolution is 12 bit, the maximum PWM frequency is 4 kHz (9 bit). If both, second PWM and SPI protocol are activated, the output pin IO1 is shared between the PWM output and the SPI_SDO output of the serial interface (Interface communication interrupts the PWM output). 1.5.2. Comparator Module (ALARM Output) The comparator module consists of two comparator channels connectable to IO1 and IO2 respectively. Each of them can be independently programmed referring to the parameters threshold, hysteresis, switching direction and on/off - delay, additional a window comparator mode is available. 1.5.3. Serial Digital Interface The ZMD31050 includes a serial digital interface which is able to communicate in three different communication protocols - I2CTM, SPITM and ZACwireTM (one wire communication). In the SPI mode the pin IO2 operates as slave select input, the pin IO1 as data output. Initializing Communication After power-on the interface is for about 20ms (start window) in the state ZACwire. During the start window it is possible to communicate via the one wire interface (pin OUT). Detecting a proper request inside the start window the interface stays in the state ZACwire. This state can be left by certain commands or a new power-on. If no request happens during the start window then the serial interface switches to I2C or SPI mode Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 10/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY (depending on EEPROM settings) and the OUT pin is used as analog output or as PWM output (also depending on EEPROM settings. The start window can generally be disabled (or enabled) by a special EEPROM setting. For detailed description of the serial interfaces see "ZMD31050 Functional Description". 1.6 Voltage Regulator For ratiometric applications 3V to 5V (+/- 10%) the external supply voltage can be used for sensor element biasing. If an absolute analog output is desired then the internal voltage regulator with external power regulation element (FET) can be used. It is bandgap reference based and designed for an external supply range from Vdda + 7V to 40V. With the voltage regulator the internal supply and sensor bridge voltage can be varied between 3V and 5V. 1.7 Error Detection A check of the sensor bridge for broken wires which is done permanently by two comparators watching the input voltage of each input (between 0.5V ... VDDA-0.5V ). This error states as well as the digital errors (CRC, parity) are indicated by forcing the output voltage into the diagnostic region, which is above 97.5% and below 2.5% of the VDDA supply. The following table shows the system response for different faults. Detected fault Signature error of EEPROM Parity error of RAM Lost of bridge positive supply Lost of bridge negative supply Diagnostic level on analog out lower lower upper upper Delay of detection 1ms 1ms 1ms 1ms Open bridge connection upper 1ms Table 6: System response for different diagnostic faults The ZMD31050 detects various possible errors. A detected error is signalized by changing into a diagnostic mode. In this case the analog output is set to High or Low (maximum or minimum possible output value) and the output registers of the digital serial interface are set to a significant error code (see Table 7). Note that the error detection functionality (except the CRC-check regarding the EEPROM content) has to be enabled by configuration words. Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 11/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet Detectable Error CRC-Error Description Sets SIF-Out to CAAA PRELIMINARY Sets Analog Out to Diagnostic Mode Low CRC-Check during read out of EEPROM after Power On or after SIF-Command COPY_EEP2RAM Parity-Check at every RAM access (Enabled by CFGAPP:SCCD) Permanent Parity-Check of Configuration Registers (Enabled by CFGAPP:SCCD) Connection-Check of Sensor Bridge (Enabled by CFGAPP:SCCD) RAM Parity Error Register Parity Error CF0F CE38 Low Low Sensor Connection CFCF E000 + VCM,13bit VCM,13bit: Measured Common Mode Voltage (13 significant Bits) High High Common Mode Voltage Check if Bridge Common Mode Voltage out of limits is complies the programmed limits (Enabled by CFGCYC:ECMV) Table 7:Error Codes Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 12/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 2. Application Circuit Examples ZMD 31050 ZMD 31050 Example 1 Typical ratiometric measurement with voltage output, temperature compensation via external diode, internal VDD regulator and supply lost diagnosis (bridge must not be at VDDA) is used Example 2 0-10V output configuration, supply regulator, temperature compensation via internal diode, internal VDD regulator and bridge in voltage mode ZMD 31050 ZMD 31050 Example 4 Example 3 Absolute voltage output, constant current biasing Ratiometric measurement, 3 - wire connection of the sensor bridge, temperature compensation for end of line calibration of the sensor module, temperature measurement with external by bridge voltage drop measurement voltage divider incl. thermistor 3. ESD/Latch-Up-Protection All Pins have an ESD Protection of >2000V (except the Pins INN,INP,FBP with > 1200V) and a Latch-up protection of 100mA or of +8V/ -4V (to VSS/VSSA). ESD Protection referred to the human body model is tested with devices in SSOP16 packages during product qualification. The ESD test follows the human body model with 1.5kOhm/100pF based on MIL 883, Method 3015.7. Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 13/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 4. Pin Configuration and Package Name OUT FBP FBN VDDA VDD VSS SCL SDA VINP VINN VBR IN3 Description Analog output & PWM1/Frequ. Output &one wire interface i/o Positive feedback connection output stage Remarks Analog output & dig. out after power on Analog input/output Pin-No. 10 11 9 1 8 15 6 7 14 16 13 2 12 3 4 5 Negative feedback connection output stage & crystal Analog input/output connection pin for Frequ. Output Positive analog supply voltage Supply Positive digital supply voltage Negative supply voltage IC clock & SPI clock Data i/o for IC & data in for SPI Positive input sensor bridge Negative input sensor bridge Bridge top sensing in bridge current out Supply Ground Digital input, pull-up Digital input, pull-up Analog input Analog input Analog input/output Analog input Analog in/out Analog output Digital IO Digital IO Resistive temperature sensor input & external clock input IR_TEMP Current source resistor i/o & temp. diode in VGATE IO1 IO2 Gate voltage for external regulator FET SPI data out & ALARM1 & PWM2 Output SPI chip select & ALARM2 The standard package of the ZMD31050 is a SSOP16 (5.3mm body width) with lead-pitch 0.65mm: FBN OUT FBP IR_TEMP VBR VINP VSS VINN VDD SDA SCL IO2 IO1 VGATE IN3 VDDA Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 14/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 5. 5.1 No. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 IC Characteristics Absolute Maximum Ratings Parameter Digital Supply Voltage Analog Supply Voltage Voltage at all analog and digital I/O - Pins Voltage at Pin FBP Storage temperature Symbol VDDAMR VDDAAMR VINA, VOUTA VFBP,AMR TSTG min -0.3 -0.3 -0.3 -1.2 -45 typ max 6.5 6.5 VDDA +0.3 VDDA +0.3 150 Unit V V V V C Conditions to VSS to VSS Exception s. 5.1.4 4 .. 20mA - Interface 5.2 No. 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 Operating Conditions Parameter Ambient temperature Ambient temperature advanced performance Analog Supply Voltage Digital Supply Voltage External Supply Voltage Common mode input range Input Voltage Pin FBP Sensor Bridge Resistance Symb ol TAMB TADV VDDA VDD 2.6 Vsupp VDDA + 2V VINCM VIN,FBP RBR 0.25 -1 3.0 2 5.0 40 min -40 -25 2.7 typ max 125 85 5.5 1.05 Unit C C V VDDA V V (Voltages related to VSS) Conditions Ratiometric mode In voltage regulator mode with external JFET absolute ratings in temperature range1 5.2.6 5.2.7 5.2.8 0.65 VDDA 25.0 VDDA V k full temperature range 4 .. 20mA - Interface 1 2 See also chapter 1.3.1 no limitations with an external connection between VDDA and VBR Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 15/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 5.2.9 Reference Resistor for Bridge Current Source RRef CVDDA CVDD CLout RLout 2 0.07 50 03 100 100 470 470 50 RBR nF nF nF k PRELIMINARY ( leads to IBR = VDDA / (16*RRef)) between VDDA and VSS, extern between VDD and VSS, extern Voltage mode Voltage mode, without supply voltage lost diagnosis 0.5...4.5V mode, with supply voltage lost diagnosis 5.2.10 Stabilization Capacitor 5.2.11 Optional Stabilization Capacitor 5.2.12 Maximum allowed load capacitance4 5.2.13 Minimum allowed load resistance 5.2.14 Minimum allowed load resistance RLout 2 25 k 5.3 No. Build In Characteristics Parameter Symbol VINSP min 1 typ max 275 Unit Conditions 5.3.1. Selectable Input Span, Pressure Measurement 5.3.2 Selectable AnalogOffset Compensation Range A/D Resolution D/A Resolution PWM - Resolution Reference current for external temperature diodes Sensitivity internal temperature diode mV/V 4 Bit setting s. 3.3.1 -300% +300% V InputSpan 6 Bit setting 5.3.3 5.3.4 5.3.5 5.3.6 RESAD RESDA RESPWM ITSE 9 11 9 10 18 15 Bit Bit 3 Bit setting @ analogue output 12 30 Bit A 5.3.7 ST,TSI 2800 3200 3600 ppm Raw values - without f.s. /K conditioning 3 4 too small stabilization capacitors can increase noise level at the output if used, consider special requirements of OWI single wire interface stated in Appendix A Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 16/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 5.3.8 Cycle Rate versus A/D-Resolution ( linear related to master clock frequency5 - values calculated at exact 2 MHz ) ADC Order Resolution Bit 9 10 11 12 13 14 15 11 12 13 14 15 Conversion Cycle fcon Hz 1302 781 434 230 115 59 30 3906 3906 1953 1953 977 PRELIMINARY 1 2 5.3.9 PWM Frequency PWM Resolution Bit 9 10 11 12 5 PWM Freq./Hz at 2 MHz Clock5 Clock Divider 1 0,5 0,25 0,125 3906 1953 977 488 1953 977 488 244 977 488 244 122 488 244 122 61 Internal RC - Oscillator: coarse adjustment to1, 2 and 4 MHz, fine tuning +/- 25% , external clock is also possible Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 17/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 5.4 No. Electrical Parameters Parameter Symbol min typ max Unit PRELIMINARY (Voltages related to VSS) Conditions 5.4.1 Supply / Regulation 5.4.1.1 Supply current ISUM 2.5 3.5 mA without bridge current and without load current, fclk 2.2MHz Without bridge current, fclk 1.2MHz, BiasAdjustment 1 5.4.1.2 Supply current for current loop 5.4.1.2 Temperature Coeff. Voltage Reference 1 IS_CL 2.0 2.5 TCREF -200 +/- 50 200 ppm/K 5.4.2 Analog Front End 5.4.2.1 Parasitic differential input offset current1 IIN -2 -10 2 10 nA temp. range 5.2.2., TADV 5.4.3 DAC & Analog Output (Pin OUT) 5.4.3.1 Signal output range VOUT 0.025 0.975 VDDA Voltage mode, assuming the maximal load of 2k 5.4.3.2 Slew rate 1 5.4.3.3 Short circuit current limitation No. Parameter SROUT ImaxOUT Symbol 0.1 5 min 10 typ 20 max V/s mA Unit Voltage mode, CL<20nF Conditions 5.4.4 PWM Output (Pin OUT, IO1) 5.4.4.1 PWM high voltage 5.4.4.2 PWM low voltage 5.4.4.3 PWM output slope1 PWMVH PWMVL PWMSL 15 0.9 0.1 VDDA VDDA V/s RL > 10 k RL > 10 k CL < 1nF 5.4.5 Temperature Sensors (Output IRT) 5.4.5.1 Sensitivity external diode or resistor meas. 1 STTSE 1450 1520 1590 ppm f.s. / mV Raw values - without conditioning no measurement in serial production, parameter is guarantied by design and/or quality observation Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 18/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 5.4.6 Digital Outputs (IO1, IO2,OUT in digital mode) 5.4.6.1 Output-High-Level 5.4.6.2 Output-Low-Level 5.4.6.3 Output Current1 VOUTP,H VOUTP,L IOUTP 4 0.9 0.1 VDDA VDDA mA PRELIMINARY 5.4.7 System Response 5.4.7.1 Setup time* 1 tIN 2 5 ms Power up to first measure result at output, without OWI - start window 5.4.7.2 Response time 5.4.7.2 Overall accuracy tRES OA 2/fCON 3/fcon Deviation from ideal line including INL, gain and offset errors -25...+85C oper. temp. -40...+125C op. temp. shorted inputs, bandwith 2kHz ratiometric input signals 0.1% 0.25% 5.4.7.3 Peak-to-PeakNoise@output 5.4.7.4 Ratiometricity Error 5.5 Interface Characteristics 5.5.1 Multiport Serial Interfaces (I2C, SPI) 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 Input-High-Level Input-Low-Level Output-Low-Level LO SDA Clock frequency SCL VIH VIL VOL CL,SDA fSCL 0.7 0 1 0.3 0.1 400 400 VDDA VDDA VDDA pF kHz 0.05 0.08 0.2 0.75 ROWI,pu RE 5 500 mV ppm * Depends on resolution and configuration - start routine begins approximately 0.8ms after power on Open-Drain, IOL = -3mA 5.5.2 One Wire Serial Interface (ZACwire) 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 Pull up resistance master OWI line resistance OWI load capacitance Voltage level Low Voltage level High ROWI,pu ROWI,line COWI,load VOWI,low VOWI,high 330 tBIT / 20s < tBIT < 100s ROWI,pu VDD VDD Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 19/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 6. Test Parameters given in this specification are design objectives. Final parameters which will be tested during series production will be specified by ZMD after investigations in the engineering samples. The resulting data sheet includes all parameters which will be tested by ZMD. The test program is based on this data sheet. The fulfillment of the test specification is obligatory to deliver and obligates to purchase. See ZMD31050 Test Description for a detailed test flow and test conditions. 7. Reliability A reliability investigation according to the in-house non-automotive standard will be performed. 8. Customization For high-volume applications, which require an up- or downgraded functionality compared to the ZM31050, ZMD can customize the circuit design by adding or removing certain functional blocks. For it ZMD has a considerable library of sensor-dedicated circuitry blocks. Thus ZMD can provide a custom solution quickly. Please contact ZMD for further information. 9. * * * * * * Related Documents ZMD31050 Feature Sheet ZMD31050 Functional Description ZMD31050 Application Kit Description ZMD31050 Development Status Report (including parts identification table) ZMD31050 Test Flow Description ZMD31050 Calibration DLL Description The information furnished here by ZMD is believed to be correct and accurate. However, ZMD shall not be liable to any licensee or third party for any damages, including, but not limited to, personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental, or consequential damages of any kind in connection with or arising out of the furnishing, performance, or use of this technical data. No obligation or liability to any licensee or third party shall result from ZMD's rendering of technical or other services. For further information: ZMD Stuttgart Office Nord-West-Ring 34 70974 Filderstadt - Bernhausen Tel.: +49 (0)711.674.517-0 Fax: +49 (0)711.674.517-99 sales@zmd.de www.zmd.biz ZMD AG Grenzstrasse 28 01109 Dresden, Germany Tel.: +49 (0)351.8822.310 Fax: +49 (0)351.8822.337 sales@zmd.de www.zmd.biz ZMD America Inc. 201 Old Country Road, Suite 204 Melville, NY 11747 Tel.: (631) 549-2666 Fax: (631) 549-2882 sensors@zmda.com www.zmd.biz Copyright (c) 2004, ZMD AG, Rev. 0.7, 2004-09-02, PRELIMINARY 20/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. |
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